1. Field of the Invention
The present invention generally relates to capturing and identifying failures in memory cards and, more particularly, to testing Dual In-line Memory Modules (DIMMs) to determine the cause and location of failures in a system environment.
2. Background Description
The industry for Personal Computers (PCs), Workstations and Laptops is building high performance systems that are utilizing Synchronous Dynamic Random Access Memories (SDRAMs). As central processing units (CPUs) become faster, memory buses must be implemented to operate at higher speeds so as not to bottleneck the system. Memory card designers are designing pluggable synchronous memory assemblies, such as Dual In-Line Memory Modules (DIMMs), to operate at synchronous memory bus speeds of 66 MHz and above.
Product engineers are required to identify root cause synchronous memory fails in real time systems. Software can be used to exercise the memory and capture the fail. This might takes months for the product engineer to capture actual cycle or multiple cycles that cause the fail. A significant risk to this method is that the software may not capture the fail. Processors have become too complex for the software to control the hardware by stepping cycles.
A memory module tester can not duplicate the exact conditions in which these Synchronous DIMMs fail. Therefore, Synchronous memory card assemblies need more tools that will capture memory fails in their actual environments.
Product engineers for synchronous memories assemblies (such as DIMMs) utilize adapter cards to characterize memory timings and analyze synchronous memory fails in computing systems such as PCs, Workstations and Laptops. Present adapter cards cause system failures in systems with memory bus timings at 100 MHz and above, mostly due to the additional wire lengths introduced with the adapter card. In systems using EDO (extended data out) memory, timings have traditionally been sufficiently lenient to permit the insertion of a module adapter card. With 66 MHz SDRAM DIMMs, margins are sufficiently tight that fails are sometimes introduced using a traditional adapter card. At 100 MHz and above, better solutions are needed.
It is therefore an object of the invention to provide a Synchronous DRAM memory test assembly that converts a normal PC or Workstation with a synchronous bus into a memory tester. This test assembly architecture supports memory bus speeds of 66 MHz and above, and provides easy access for a logic analyzer. The test assembly supports Registered and Unbuffered Synchronous DRAM DIMM products.
It is another object of the invention to provide a test assembly that re-drives the system clocks with a phase lock loop (PLL) buffer to a DIMM socket on the test assembly to permit timing adjustments to minimize the degradation to the system""s memory bus timings due to the additional wire length.
The present invention permits good and questionable synchronous modules to be compared on card and the results captured using an external logic analyzer. It permits resolution of in-system fails that occur uniquely in system environments.
According to the invention, the test assembly is programmable to adjust to varying bus timings such as CAS (column address strobe) Latencies and Burst Length variations. It captures and displays the last valid Mode Register Set programmed by the system while under test. The test assembly compares data on Read and Write cycles. Data paths, such as System Data, Test Data and Error Data, can be observed. The test assembly captures and displays the device address for the current access. Field Programmable Gate Arrays (FPGAs) are utilized to allow for changes internally without modifying the test assembly.
The test assembly may be split into two segments: a diagnostic card and an adapter card. The diagnostic card is connected to the DIMM sockets via an adapter card to limit mechanical load on the system socket as well as permit varying form factors. The diagnostic card may be powered via the system power supply or an external power supply. It also provides a bit map capability to identify the failing device on the DIMM.
The test assembly provides failure information in real time via the logic analyzer display. A logic analyzer is connected to the diagnostic card via cables. The product engineer can monitor device fails under actual operating conditions via the logic analyzer. Any use of the invention will require that the user has a memory module that is suspected of causing a failure in a PC application. First the adapter card must be installed in a memory socket of the PC. The suspect memory module may be installed in either the system socket of the adapter card or the test socket. If the system socket is used, the memory faults will cause aberrant behavior in the PC application, perhaps a line of diagnostic output in a test program or a system crash in a non-robust application. This will allow for rough visual correlation between that failure event and an error detected by the present invention in that the light emitting diodes (LEDs) will light or the Logic Analyzer will trigger at the same time the PC shows the fault. If the suspect module is installed in the test socket, the PC application will not show the fault, but will indicate that a memory failure has occurred. One skilled in the art of diagnosing memory fails will understand to connect their logic analyzer in a fashion meaningful to the problem at hand and to receive the type of information required.